Programmable Hardware

index, Hardware Design, research,

This material unexhaustively documents my thesis work in progress on Reconfigurable computing on FPGA.

1 Documents

2012-06-21 ThuDiploma thesis final version (English): Self-reconfiguring System-on-Chip using Linux on a Virtex-5 FPGA, also available at the HU edoc-Server
2012-01-19 ThuDiploma thesis presentation slides (German)
2011-12-21 WedCode Repository for thesis work
2010-11-04 ThuVery quick Partial reconfiguration on embedded Linux on Xilinx Virtex5 FPGA Tutorial
2010-06-03 ThuSeminar Talk, slightly modified version of the slides referenced below: Audio-processing on FPGA #2 (still in German :)
2010-04-22 ThuSeminar Project report: Audio-Processing on FPGA (in German)

2 Tools under investigation

  • Xilinx toolchain
  • MyHDL
  • PyXDL
  • bitinfo
  • debit
  • RapidSmith / Torc
  • FAT


[1] 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 12-14 July 2001, Long Beach, CA, USA. IEEE Computer Society, 2001. [ bib ]
[2] 4th NASA / DoD Workshop on Evolvable Hardware (EH 2002), 15-18 July 2002, Alexandria, VA, USA. IEEE Computer Society, 2002. [ bib ]
[3] 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA. IEEE Computer Society, 2005. [ bib ]
[4] Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006. IEEE, 2006. [ bib ]
[5] Chatchawit Aporntewan and Prabhas Chongstitvatana. A hardware implementation of the compact genetic algorithm. In IEEE Congress on Evolutionary Computation, pages 624-629, 2001. [ bib ]
[6] W. Ross Ashby. The W. Ross Ashby Digital Archive, Mar 1948. [ bib | .html ]
[7] W. Ross Ashby. Design for a Brain. Chapman and Hall, 1952. [ bib ]
[8] John Aycock. Compiling Little Languages in Python. Technical report, Department of Computer Science, University of Victoria, Victoria, B.C., Canada, 2000. [ bib ]
[9] Salih Bayar and Arda Yurdakul. Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port (PCAP), volume 8, page 1–10. Citeseer, 2008. [ bib | http ]
[10] Joachim Becker. A Hexagonal Lattice Continuous-Time Field Programmable Analog Array and Filter Synthesis through Genetic Algorithm. PhD thesis, Department of Microsystems Technology (IMTEK), University of Freiburg, 2007. [ bib ]
[11] Tobias Becker, Wayne Luk, and Peter Y. K. Cheung. Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. In Pocek and Buell [105], pages 35-44. [ bib ]
[12] P. Bellows and B. Hutchings. JHDL - An HDL for Reconfigurable Systems. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, FCCM '98, pages 175-, Washington, DC, USA, 1998. IEEE Computer Society. [ bib | http ]
[13] Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, and Stamatis Vassiliadis, editors. FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007. IEEE, 2007. [ bib ]
[14] Oswald Berthold. Hybride Rechenmedien. Website, 2011. [ bib | .pdf ]
[15] J. Bird and P. Layzell. The evolved radio and its implications for modelling the evolution of novel sensors. In Proceedings of the Evolutionary Computation on 2002. CEC '02. Proceedings of the 2002 Congress - Volume 02, CEC '02, pages 1836-1841, Washington, DC, USA, 2002. IEEE Computer Society. [ bib | .pdf ]
[16] Brandon Blodget, Philip James-Roxby, Eric Keller, Scott Mcmillan, and Prasanna Sundararajan. A self-reconfiguring platform. In In Proceedings of Field Programmable Logic and Applications (2003, pages 565-574, 2003. [ bib ]
[17] Christophe Bobda. Introduction to Reconfigurable Computing. Springer, 2007. [ bib ]
[18] Martin Brückner. Linux auf FPGA-Hardware zur Bildverarbeitung, 2007. Student research project. [ bib | .pdf ]
[19] Marian Bubak, G. Dick van Albada, Peter M. A. Sloot, and Jack Dongarra, editors. Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III, volume 3038 of Lecture Notes in Computer Science. Springer, 2004. [ bib ]
[20] Poki Chen, Chun-Yan Chu, Mon-Chau Shie, Zi-Fan Zheng, and Zhi-Yuan Zheng. A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements. IEEE Transactions On Circuits And Systems—I: Regular Papers, 54(12):2661-2668, Dec. 2007. [ bib ]
[21] Leon O. Chua. Memristor - The Missing Circuit Element. IEEE Transactions on circuit Theory, CT18(5), 1971. [ bib ]
[22] Christopher Claus, Florian Helmut Müller, and Walter Stechele. Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. In Karl et al. [59], pages 122-131. [ bib | .html ]
[23] Community. Xilinx linux kernel tree. git:// [ bib ]
[24] Sesh Commuri, V. Tadigotla, and L. Sliger. Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs. J. Intell. Robotics Syst., 49:111-134, June 2007. [ bib | DOI | http ]
Keywords: FPGA, autonomous ground vehicles, fault-tolerance, hardware reconfiguration, intelligent robots
[25] Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees Vissers, and Zhiru Zhang. High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Transactions on Computer Aided Design (TCAD), 30(4):473-491, April 2011. Invited Keynote, to appear. [ bib ]
[26] S. Corbetta, F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, and D. Sciuto. Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 457-458, Washington, DC, USA, 2007. IEEE Computer Society. [ bib | DOI | http ]
[27] Guillaume Dargaud. Embedded Linux on Xilinx ML405 card: A Tutorial, April 2008. Referring to online version of 20101104. [ bib | .html ]
[28] Hugo de Garis, Andy Tyrrell, Pauline Haddow, Nicholas Macias, Lisa Durbeck, John Koza, Andrés Upegui, Carlos Andrés Peńa-Reyes, Eduardo Sánchez, Lukas Sekanina, Esther Hughes, Sharon Graves, Tim Gordon, Srivallaba Mysore, Yuya Sasaki, and Ravichandra Sriram. The XILINX Club - A World Survey of Evolvable Hardware Research Projects Using Xilinx's Programmable FPGA Chips. Xilinx.doc. [ bib ]
[29] Jan Decaluwe. MyHDL manual. [ bib | .pdf ]
[30] Rolf Drechsler and Nicole Drechsler. GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. In Raidl et al. [108], pages 378-387. [ bib ]
[31] R. T. Edwards, K. Strohbehn, S. E. Jaskulek, and R. Katz. Analog module architecture for space-qualified field-programmable mixed-signal arrays. In Proceedings of the 2nd annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), 1999. [ bib ]
[32] G. Estrin and C. R. Viswanathan. Organization of a “Fixed-Plus-Variable” Structure Computer for Computation of Eigenvalues and Eigenvectors of Real Symmetric Matrices. J. ACM, 9:41-60, January 1962. [ bib | DOI | http ]
[33] Gerald Estrin. Organization of computer systems: the fixed plus variable structure computer. In Papers presented at the May 3-5, 1960, western joint IRE-AIEE-ACM computer conference, IRE-AIEE-ACM '60 (Western), pages 33-40, New York, NY, USA, 1960. ACM. [ bib | DOI | http ]
[34] Gerald Estrin. Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer. IEEE Ann. Hist. Comput., 24:3-9, October 2002. [ bib | DOI | http ]
[35] John R. Koza et al. Genetic Programming IV - Routine Human-Competitive Machine Intelligence. Kluwer, 2003. [ bib ]
[36] David B. Fogel. Evolutionary Computation. IEEE Press, 2000. [ bib ]
[37] Xilinx User Community Forum. PlanAhead error on IDELAY_VALUE=35 constraint, Nov. 2010. [ bib | http ]
[38] Xilinx User Community Forum. ICAP destroy FPGA?, Dec. 2011. [ bib | http ]
[39] M. D. Godfrey and D. F. Hendry. The Computer as von Neumann Planned It. IEEE Ann. Hist. Comput., 15:11-21, January 1993. [ bib | DOI | http ]
[40] Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, and Walild Najjar. A Compiler Intermediate Representation for Reconfigurable Fabrics. International Journal of Parallel Programming, 36:493-520, 2008. 10.1007/s10766-008-0080-7. [ bib | http ]
[41] Pauline C. Haddow and Gunnar Tufte. Bridging The Genotype-Phenotype Mapping For Digital FPGAs. In Evolvable Hardware [1], pages 109-115. [ bib ]
[42] Pauline C. Haddow and Andy M. Tyrrell. Challenges of evolvable hardware: past, present and the path to a promising future. Genetic Programming and Evolvable Machines, 12:183-215, September 2011. [ bib | DOI | http ]
Keywords: Computation medium, Evolvable hardware, Future technology, Review, Scalability
[43] Jens Hagemeyer, Boris Kettelhoit, Markus Koester, and Mario Porrmann. Design of homogenous communication infrastructures for partially reconfigurable FPGAs. Proceedings of the 2007 Intl. Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), 2007. [ bib ]
[44] Sverre Hamre. Framework for self reconfigurable system on a Xilinx FPGA. Master's thesis, NTNU - Norwegian University of Science and Technology, 2009. [ bib ]
[45] S. Harding and J.F. Miller. Evolution in materio: a tone discriminator in liquid crystal. In Evolutionary Computation, 2004. CEC2004. Congress on, volume 2, pages 1800-1807 Vol.2, 2004. [ bib | http ]
Intrinsic evolution in evolvable hardware research has hitherto been limited to using standard electronic components as the media for problem solving. However, recently it has been argued that because such components are human designed and intentionally has predictable responses; they may not be the optimal medium to use when trying to get a naturally inspired search technique to solve a problem. Evolution has been demonstrated as capable of exploiting the physical properties of material to form solutions; however, by giving evolution only conventional components, we may be placing arbitrary constraints on our ability to solve certain problems. We have shown for the first time, that liquid crystal can be used as the physical substrate for evolution. We demonstrate that it is possible to evolve various functions, including a tone discriminator, in materio.

Keywords: arbitrary constraints,circuit optimisation,electronic components,evolutionary computation,evolvable hardware,intrinsic evolution,liquid crystal,liquid crystal displays,liquid crystals,logic circuits,problem solving,problem solving media,search problems,search technique,tone discriminator
[46] Simon Harding, Julian F. Miller, and Wolfgang Banzhaf. Evolution, development and learning with self modifying cartesian genetic programming. In GECCO '09: Proceedings of the 11th Annual conference on Genetic and evolutionary computation, pages 699-706, New York, NY, USA, 2009. ACM. [ bib | DOI | http ]
[47] R.W. Hartenstein, A.G. Hirschbiel, and M.Weber. Xputers - An Open Family of Non von Neumann Architectures. In Proc. of 11th ITG/GI-Conference: Architektur von Rechensystemen. VDE-Verlag, 1990. [ bib ]
[48] Inman Harvey. Artificial evolution and real robots. Artificial Life and Robotics, 1:35-38, 1997. [ bib ]
[49] Inman Harvey, Phil Husbands, and Dave Cliff. Seeing the light: Artificial evolution, real vision, 1994. [ bib ]
[50] Inman Harvey and Adrian Thompson. Through the labyrinth evolution finds a way: A silicon ridge. In Higuchi et al. [51], pages 406-422. [ bib ]
[51] Tetsuya Higuchi, Masaya Iwata, and Weixin Liu, editors. Evolvable Systems: From Biology to Hardware, First International Conference, ICES 96, Tsukuba, Japan, October 7-8, 1996, Proceedings, volume 1259 of Lecture Notes in Computer Science. Springer, 1996. [ bib ]
[52] John H. Holland. Adaptation in Natural and Artificial Systems. The University of Michigan Press, 1975. [ bib ]
[53] Edson L. Horta and John W. Lockwood. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs). [ bib | http ]
Field Programmable Gate Arrays (FPGAs) can be partially reconfigured to implement Dynamically loadable Hardware Plugin (DHP) modules. A tool called PARBIT has been developed that transforms FPGA configuration bitfiles to enable DHP modules. With this tool it is possible to define a partial reconfigurable area inside the FPGA and download it into a specified region of the FPGA device. One ore more DHPs, with different sizes can be implemented using PARBIT. Supported by: NSF ANI-0096052, Xilinx...

Keywords: fpga
[54] Michael Hubner, Lars Braun, Jurgen Becker, Christopher Claus, and Walter Stechele. Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 41-46, Washington, DC, USA, 2007. IEEE Computer Society. [ bib | DOI | http ]
[55] Sean V. Hum and Robert J. Davies. An evolvable antenna platform based on reconfigurable reflectarrays. In Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware, pages 139-146, Washington, DC, USA, 2005. IEEE Computer Society. [ bib | DOI | http ]
[56] Mike Hutton and Paul Chow, editors. Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. ACM, 2008. [ bib ]
[57] Texas Instruments. OMAP3503/15 ARM Cortex-A8 Perf. Line, Jan. 2011. [ bib | http ]
[58] C. Richard Johnson Jr. and William A. Sethares. Telecommunication Breakdown - or How I Learned to Stop Worrying and Love the Digital Radio. Prentice Hall, 2003. [ bib | .pdf ]
[59] Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, and Erik Maehle, editors. ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany, volume 81 of LNI. GI, 2006. [ bib ]
[60] John H. Kelm. Running Linux on a Xilinx XUP Board. Technical report, University of Illinois at Urbana-Champaign, Department of Computer Engineering, 2006. [ bib ]
[61] Krzysztof Kepa, Fearghal Morgan, Krzysztof Kościuszkiewicz, Lars Braun, Michael Hübner, and Jürgen Becker. FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. In Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications, ARC '09, pages 62-73, Berlin, Heidelberg, 2009. Springer-Verlag. [ bib | DOI | http ]
Keywords: EDA tools, FPGA, Reconfigurable Computing, bitstream debugging, design assurance, design verification, security
[62] Peter Korsgaard. Buildroot: making Embedded Linux easy., Dec. 2010. [ bib | http ]
[63] John R. Koza. Genetic Programming. MIT Press, 1992. [ bib ]
[64] Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, and Didier Joly. Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. In FPL [4], pages 1-4. [ bib ]
[65] David Krutz. Konzeption einer hierarchischen Strukturgenerierung zur Realisierung von abstrakten Hardwareschnittstellen, 2002. [ bib ]
[66] David Krutz. Ein Betriebssystem für konfigurierbare Hardware. PhD thesis, Humboldt-Universität zu Berlin, 2007. [Online: Stand 2012-01-20T09:44:04Z]. [ bib | http ]

Keywords: englishheterogeneous system, operating system, VHDL, FPGA
[67] Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent Nelson, Brad Hutchings, and Mike Wirthlin. Using Hard Macros to Reduce FPGA Compilation Time. In Proceedings of the 20th International Workshop on Field-Programmable Logic and Applications (FPL'10), August 2010. [ bib ]
[68] Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson, Brad Hutchings, and Michael Wirthlin. RAPIDSMITH - a library for low-level manipulation of partially placed-and-routed fpga designs. Technical report, NSF Center for High Performance Reconfigurable Computing (CHREC), 2011. Part of RapidSmith Documentation: rapidSmith/doc/TechReportAndDocumentation.pdf. [ bib ]
[69] Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent Nelson, and Brad Hutchings. Rapid Prototyping Tools for FPGA Designs: RapidSmith. In Field-Programmable Technology (FPT'10). International Conference on, December 2010. [ bib ]
[70] Delon Levi and Steven A. Guccione. GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices. In Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware, EH '99, pages 12-, Washington, DC, USA, 1999. IEEE Computer Society. [ bib | http ]
[71] Derek S. Linden. Optimizing signal strength in-situ using an evolvable antenna system. In Evolvable Hardware [2], pages 147-151. [ bib ]
[72] John Linn, bones, and Julie Zhu. Xilinx Open Source Wiki, Nov. 2010. [ bib | http ]
[73] Shih-Chii Liu, Jorg Kramer, Giancomo Indiveri, Tobias Delbruck, Rodney Douglas, and Carver A. Mead. Analog VLSI: Circuits and Principles. MIT Press, 2002. [ bib ]
[74] Matthias Lorenz. Synthese analoger Filter durch genetische Programmierung - Anwendung auf einer FPAA-basierenden Hardwareplattform. Studienarbeit, 2009. [ bib ]
[75] Mateusz Majer, Jürgen Teich, Ali Ahmadinia, and Christophe Bobda. The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer, 2007. [ bib ]
[76] Philippe Manet, Daniel Maufroid, Leonardo Tosi, Gregory Gailliard, Olivier Mulertt, Marco Di Ciano, Jean-Didier Legat, Denis Aulagnier, Christian Gamrat, Vincenzo La Barba Raffaele Liberati, Pol Cuvelier, Bertrand Rousseau, and Paul Gelineau. An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications. EURASIP Journal on Embedded Systems, 2008. [ bib ]
[77] Daniel Mange, André Stauffer, and Gianluca Tempesti. Toward robust integrated circuits: The embryonics approach. In Proceedings of the IEEE, pages 516-541, 2000. [ bib ]
[78] Tomás Martínek and Lukás Sekanina. An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA. In Moreno et al. [86], pages 76-85. [ bib ]
[79] Carver Mead. Analog VLSI and Neural Systems. Addison-Wesley, 1989. [ bib ]
[80] Michael Menz. Realisierung von global asynchronen und lokal synchronen Strukturen auf programmierbaren Logikschaltungen mit verschiedenen Clock-Domains, 2006. [ bib ]
[81] Grégory Mermoud. A Module-Based Dynamic Partial Reconguration tutorial. Technical report, Logic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, 2004. [ bib ]
[82] Julian F. Miller, Adrian Thompson, Peter Thomson, and Terence C. Fogarty, editors. Evolvable Systems: From Biology to Hardware, Third International Conference, ICES 2000, Edinburgh, Scotland, UK, April 17-19, 2000, Proceedings, volume 1801 of Lecture Notes in Computer Science. Springer, 2000. [ bib ]
[83] Melanie Mitchell and Charles E. Taylor. Evolutionary Computation: An Overview. Annu. Rev. Ecol. Syst., 1999. [ bib ]
[84] Juan Carlos Moctezuma Eugenio and Miguel Arias Estrada. Hardware/Software FPGA Architecture for Robotics Applications. In Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications, ARC '09, pages 27-38, Berlin, Heidelberg, 2009. Springer-Verlag. [ bib | DOI | http ]
[85] Federico Morán, Alvaro Moreno, Juan J. Merelo Guervós, and Pablo Chacón, editors. Advances in Artificial Life, Third European Conference on Artificial Life, Granada, Spain, June 4-6, 1995, Proceedings, volume 929 of Lecture Notes in Computer Science. Springer, 1995. [ bib ]
[86] Juan Manuel Moreno, Jordi Madrenas, and Jordi Cosp, editors. Evolvable Systems: From Biology to Hardware, 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005, Proceedings, volume 3637 of Lecture Notes in Computer Science. Springer, 2005. [ bib ]
[87] Andreas Mäder. VHDL Kompakt. Universität Hamburg, 2010. [ bib | .pdf ]
[88] Federico Nava, Donatella Sciuto, Marco D. Santambrogio, Stefan Herbrechtsmeier, Mario Porrmann, Ulf Witkowski, and Ulrich Rückert. Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms. TRETS, 4(3):29, 2011. [ bib ]
[89] Nadia Nedjah and Luiza de Macedo Mourelle. An efficient problem-independent hardware implementation of genetic algorithms. Neurocomputing, 71(1–3):88 - 94, 2007. Dedicated Hardware Architectures for Intelligent Systems, Advances on Neural Networks for Speech and Audio Processing. [ bib | DOI | http ]
Keywords: Genetic algorithms
[90] Stephen Neuendorffer. Generic partially reconfigured processor systems applied to software defined radio. In Proceeding of the SDR 07 Technical Conference and Product Exposition, 2007. [ bib ]
[91] Stefano Nolfi and Dario Floreano. Evolutionary Robotics. MIT Press, 2000. [ bib ]
[92] Jean-Baptiste Note and Éric Rannaud. From the bitstream to the netlist. In Hutton and Chow [56], page 264. [ bib ]
[93] OpenCores. OpenCores Website, Jun. 2010. [ bib | http ]
[94] OpenEmbedded Developers. Openembedded, the build framework for embedded linux., Jan. 2011. [ bib | http ]
[95] Björn Osterloh, Harald Michalik, Sandi Alexander Habinc, and Björn Fiethe. Dynamic partial reconfiguration in space applications. In Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems, AHS '09, pages 336-343, Washington, DC, USA, 2009. IEEE Computer Society. [ bib | DOI | http ]
Keywords: SoCWire, dynamic, partial, reconfiguration, Leon3, space, spacewire, virtex
[96] Nicholas Palladino. Wiki for the Computer Engineering department's FPGA cluster at RIT., Dec. 2010. [ bib | http ]
[97] Kyprianos Papadimitriou, Antonis Anyfantis, and Apostolos Dollas. An Effective Framework to Evaluate Dynamic Partial Reconfiguration in FPGA Systems. IEEE T. Instrumentation and Measurement, 59(6):1642-1651, 2010. [ bib ]
[98] Gordon Pask. Physical Analogues to the Growth of a Concept. In A. Uttley, editor, Mechanisation of Thought Processes, pages 877-922. HMSO London, 1959. [ bib | .pdf ]
[99] Gordon Pask. The Natural History of Networks. In Yovits and Cameron [151], pages 232-263. [ bib | http ]
[100] Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, and Jürgen Becker. Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. In Bertels et al. [13], pages 351-356. [ bib ]
[101] Rolf Pfeifer and Josh Bongard. How the Body Shapes the Way We Think. MIT Press, 2007. [ bib ]
[102] Jean-Marc Philippe, Benoît Tain, and Christian Gamrat. A self-reconfigurable FPGA-based platform for prototyping future pervasive systems. In Proceedings of the 9th international conference on Evolvable systems: from biology to hardware, ICES'10, pages 262-273, Berlin, Heidelberg, 2010. Springer. [ bib | http ]
[103] Grégory Pierre-Louis and Justin Wells. Temperature Estimation Using Ring Oscillators. Technical report, Worcester Polytechnic Institute, 2009. [ bib ]
[104] Toomas P. Plaks, editor. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04, June 21-24, 2004, Las Vegas, Nevada, USA. CSREA Press, 2004. [ bib ]
[105] Kenneth L. Pocek and Duncan A. Buell, editors. IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2007, 23-25 April 2007, Napa, California, USA. IEEE Computer Society, 2007. [ bib ]
[106] Reid B. Porter and Neil W. Bergmann. Evolving FPGA Based Cellular Automata. In Selected papers from the Second Asia-Pacific Conference on Simulated Evolution and Learning on Simulated Evolution and Learning, SEAL'98, pages 114-121, London, UK, 1999. Springer-Verlag. [ bib | http ]
[107] Anup Kumar Raghavan and Peter Sutton. JPG - A Partial Bitstream Generation Tool to Support Partial Reconfiguration in Virtex FPGAs. In Proceedings of the 16th International Parallel and Distributed Processing Symposium, IPDPS '02, pages 192-, Washington, DC, USA, 2002. IEEE Computer Society. [ bib | http ]
[108] Günther R. Raidl, Jean-Arcady Meyer, Martin Middendorf, Stefano Cagnoni, Juan J. Romero Cardalda, David Corne, Jens Gottlieb, Agnès Guillot, Emma Hart, Colin G. Johnson, and Elena Marchiori, editors. Applications of Evolutionary Computing, EvoWorkshop 2003: EvoBIO, EvoCOP, EvoIASP, EvoMUSART, EvoROB, and EvoSTIM, Essex, UK, April 14-16, 2003, Proceedings, volume 2611 of Lecture Notes in Computer Science. Springer, 2003. [ bib ]
[109] Franz J. Rammig. A concept for the editing of hardware resulting in an automatic hardware-editor. In Proceedings of the 14th Design Automation Conference, DAC '77, pages 187-193, Piscataway, NJ, USA, 1977. IEEE Press. [ bib | http ]
[110] Ingo Rechenberg. Evolutionsstrategie. Optimierung technischer Systeme nach Prinzipien der biologischen Evolution. Frommann Holzboog, 1973. [ bib ]
[111] Thomas W. Rondeau. Application of Artificial Intelligence to Wireless Communications. PhD thesis, Virginia Polytechnic Institute and State University, 2007. [ bib | .pdf ]
[112] Eduardo Sanchez and Marco Tomassini, editors. Towards Evolvable Hardware, The Evolutionary Engineering Approach, Papers from an international workshop, Lausanne, Switzerland, October 2-3, 1995, volume 1062 of Lecture Notes in Computer Science. Springer, 1996. [ bib ]
[113] Ron Sass. Reconfigurable computing system's (rcs) lab wiki., Dec. 2010. [ bib ]
[114] Patrick Schaumont, Ingrid Verbauwhede, Kurt Keutzer, and Majid Sarrafzadeh. A quick safari through the reconfiguration jungle. In In Design Automation Conference, pages 172-177. ACM Press, 2001. [ bib ]
[115] SDR Forum. SDRF Cognitive Radio Definitions, 2007. [ bib | .pdf ]
[116] D. Sheldon, R. Roosta, M. Sadigursky, and A. Farrokhy. Monitoring Temperature in SRAM-based FPGAs using a Ring-Oscillator Design, 2007. Presentation Slides, JPL and Caltech. [ bib ]
[117] Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, and Adonios Thanailakis. DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. In IPDPS [3]. [ bib ]
[118] Moshe Sipper, Daniel Mange, and Andrés Pérez-Uribe, editors. Evolvable Systems: From Biology to Hardware, Second International Conference, ICES 98, Lausanne, Switzerland, September 23-25, 1998, Proceedings, volume 1478 of Lecture Notes in Computer Science. Springer, 1998. [ bib ]
[119] Lee Spector. Automatic Quantum Computer Programming: A Genetic Programming Approach. Kluwer, 2004. [ bib ]
[120] Susan Stepney. The neglected pillar of material computation, 2008. [ bib | http ]
[121] Dmitri B. Strukov, Gregory S. Snider, Duncan R. Stewart, and R. Stanley Williams. The missing memristor found. Nature, 2008. [ bib ]
[122] Gianluca Tempesti. A Self-Repairing Multiplexer-Based FPGA Inspired by Biological Processes. PhD thesis, EPFL, 1998. [ bib ]
[123] Gianluca Tempesti, Daniel Mange, and André Stauffer. A Self-Repairing Multiplexer-Based FPGA Inspired by Biological Processes. Technical report, EPFL, 1998. [ bib ]
[124] Gianluca Tempesti, Andy M. Tyrrell, and Julian F. Miller, editors. Evolvable Systems: From Biology to Hardware - 9th International Conference, ICES 2010, York, UK, September 6-8, 2010. Proceedings, volume 6274 of Lecture Notes in Computer Science. Springer, 2010. [ bib ]
[125] Adrian Thompson. Evolving electronic robot controller that exploit hardware resources. In Morán et al. [85], pages 640-656. [ bib ]
[126] Adrian Thompson. Evolving electronic robot controllers that exploit hardware resources. In F. Morán, A. Moreno, J. J. Merelo, and P. Chacon, editors, Advances in Artificial Life: Proc. 3rd Eur. Conf. on Artificial Life (ECAL95), volume 929 of LNAI, pages 640-656. Springer-Verlag, 1995. [ bib ]
[127] Adrian Thompson. Silicon evolution. In Stanford University, pages 444-452. MIT Press, 1996. [ bib ]
[128] Adrian Thompson. An evolved circuit, intrinsic in silicon, entwined with physics. In Tetsuya Higuchi, Masaya Iwata, and L. Weixin, editors, Proc. 1st Int. Conf. on Evolvable Systems (ICES'96), volume 1259 of LNCS, pages 390-405. Springer-Verlag, 1997. [ bib ]
[129] Adrian Thompson. On the automatic design of robust electronics through articial evolution. In Moshe Sipper, Daniel Mange, and Andrés Pérez-Uribe, editors, Evolvable Systems: From Biology to Hardware Second International Conference, ICES 98 Lausanne, Switzerland, September 23–25, 1998 Proceedings, volume 1478 of LNCS, pages 13-24. Springer, 1998. [ bib ]
[130] Adrian Thompson, Inman Harvey, and Phil Husbands. Unconstrained evolution and hard consequences. In Sanchez and Tomassini [112], pages 136-165. [ bib ]
[131] Gunnar Tufte and Pauline C. Haddow. Biologically-Inspired: A Rule-Based Self-Reconfiguration of a Virtex Chip. In Bubak et al. [19], pages 1249-1256. [ bib ]
[132] A.M. Tyrrell, G. Hollingworth, and S.L. Smith. Evolutionary Strategies and Intrinsic Fault Tolerance, 2001. [ bib ]
[133] Andrés Upegui and Eduardo Sanchez. Evolving hardware by dynamically reconfiguring Xilinx FPGAs. In J.M. Moreno et al., editor, Evolvable Systems: From Biology to Hardware, volume 3637 of LNCS, pages 56-65, Berlin Heidelberg, 2005. Springer-Verlag. [ bib ]
[134] Andrés Upegui and Eduardo Sanchez. Evolving Hardware with Self-Reconfigurable Connectivity in Xilinx FPGAs. In A. Stoica et al., editor, Proceedings of the 1st NASA /ESA Conference on Adaptive Hardware and Systems(AHS-2006), pages 153-160, Los Alamitos, CA, USA, 2006. IEEE Computer Society. [ bib ]
[135] Zdenek Vasicek and Lukas Sekanina. An evolvable hardware system in Xilinx Virtex II Pro FPGA. Int. J. Innov. Comput. Appl., 1:63-73, April 2007. [ bib | DOI | http ]
Keywords: EA, FPGA, circuit architectures, evolutionary algorithms, evolvable hardware, field programmable gate arrays, image filter evolution, image operators, reconfigurable logic, search algorithms, virtual reconfigurable circuits
[136] Miguel A. Vega-Rodriguez, Raul Gutierrez-Gil, Jose M. Avila-Roman, Juan M. Sanchez-Perez, and Juan A. Gomez-Pulido. Genetic Algorithms Using Parallelism and FPGAs: The TSP as Case Study. In Proceedings of the 2005 International Conference on Parallel Processing Workshops, ICPPW '05, pages 573-579, Washington, DC, USA, 2005. IEEE Computer Society. [ bib | DOI | http ]
[137] John von Neumann. Probabilistic logics and synthesis of reliable organisms from unreliable components. In C. Shannon and J. McCarthy, editors, Automata Studies, pages 43-98. Princeton University Press, 1956. [ bib ]
[138] John von Neumann. The Computer and the Brain. Yale University Press, 1958. [ bib ]
[139] John von Neumann. Theory of Self-reproducing Automata. University of Illinois Press, 1966. edited and completed by Arthur W. Burks. [ bib ]
[140] John von Neumann. First Draft of a Report on the EDVAC. IEEE Ann. Hist. Comput., 15:27-75, October 1993. [ bib | DOI | http ]
[141] Axel Weiss. freeSP., Jan. 2011. [ bib ]
[142] Wikipedia. Reconfigurable computing, Jan 2011. [ bib | http ]
[143] Wikipedia. Von Neumann architecture, Feb 2012. [ bib | http ]
[144] John W. Williams and Neil W. Bergmann. Embedded Linux as a Platform for Dynamically Self-Reconfiguring Systems-on-Chip. In Plaks [104], pages 163-169. [ bib ]
[145] Xilinx, Inc. Xilinx UG191: Virtex-5 FPGA Configuration User Guide, Aug 2009. [ bib | .pdf ]
[146] Xilinx, Inc. Xilinx UG347: ML505/ML506/ML507 Evaluation Platform - User Guide, Oct 2009. [ bib | .pdf ]
[147] Xilinx, Inc. Virtex-5 FPGA Data Sheet: DC and Switching Characteristics, May 2010. [ bib | .pdf ]
[148] Xilinx, Inc. Xilinx UG702: Partial Reconfiguration User Guide, May 2010. [ bib | .pdf ]
[149] Xilinx, Inc. Xilinx UG743: PlanAhead Software Tutorial - Overview of the Partial Reconfiguration Flow, 2010. [ bib | .pdf ]
[150] Xilinx, Inc. Xilinx UG744: PlanAhead Software Tutorial - Partial Reconfiguration of a Processor Peripheral, 2010. [ bib | .pdf ]
[151] Marshall C. Yovits and Scott Cameron, editors. Self-organizing systems, Proceedings of an Interdisciplinary Conference, volume 2 of International Tracts in Computer Science and Technology and their Application. Pergamon Press, 1960. [ bib | http ]
[152] Z. Zhu, D.J. Mulvaney, and V.A. Chouliaras. Hardware implementation of a novel genetic algorithm. Neurocomputing, 71(1–3):95 - 106, 2007. Dedicated Hardware Architectures for Intelligent Systems, Advances on Neural Networks for Speech and Audio Processing. [ bib | DOI | http ]
Keywords: Genetic algorithms

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